Generally, a typical semiconductor device includes a substrate having active devices such as transistors and capacitors. These active devices are initially isolated from each other, and interconnect structures are subsequently formed over the active devices to create functional circuits. Generally these interconnect structures include conductive features (e.g., metal lines and vias) formed in a plurality of stacked dielectric layers. To reduce the capacitive coupling of conductive features in dielectric layers, low-k dielectric materials are generally used for interconnect layers. However, as the density of conductive features increases in these layers, traditional low-k materials may no longer sufficiently reduce capacitive coupling.
Voids may be formed in dielectric layers to further reduce the k-value of the dielectric material and reduce parasitic capacitance amongst conductive features. However, void formation in interconnect layers poses numerous challenges such as difficulties in controlling the dimensions of voids and the risk of damaging conductive features adjacent to voids during the subsequent patterning of any overlaying layers.